DocumentCode :
3001273
Title :
Systematic design optimization of a competitive soft-concatenated decoding system
Author :
Joeressen, Olaf J. ; Schneider, Gregor ; Meyr, Heinrich
Author_Institution :
Lab. for Integr. Syst. for Signal Proc., RWTH Aachen, Germany
fYear :
1993
fDate :
20-22 Oct 1993
Firstpage :
105
Lastpage :
113
Abstract :
Due to the advances in VLSI technology complete digital communication systems can today be implemented on single application specific VLSI circuits. The optimum choice of implementation parameters, such as signal wordlengths, is a critical design task since poor parameter choices can lead to costly designs. On the other hand, the high number of parameters to be selected span a large search space that is very difficult to handle. The authors present a new systematic approach to parameter selection and apply this approach to the design optimization of a decoding system for a concatenated coding scheme. Two convolutional codes are concatenated and both are decoded by soft decision decoding. This is facilitated by means of soft output decoding of the inner code. The performance of the scheme is better than that of the well known standard code with 64 states for moderate BER at equivalent implementation cost. The proposed coding scheme is thus an attractive alternative whenever high bit error rate performance is prerequisite, e.g. for digital HDTV transmission
Keywords :
CMOS logic circuits; VLSI; Viterbi decoding; application specific integrated circuits; circuit analysis computing; circuit optimisation; concatenated codes; convolutional codes; digital communication; digital signal processing chips; digital television; high definition television; integrated circuit design; logic CAD; telecommunication computing; CMOS; VHDL; Viterbi decoding; application specific VLSI; convolutional codes; digital HDTV transmission; high bit error rate performance; inner code; logic synthesis; signal wordlengths; soft decision decoding; soft output decoding; soft-concatenated decoding system; systematic design optimization; Bit error rate; Circuits; Communications technology; Concatenated codes; Convolutional codes; Decoding; Design optimization; Digital communication; Signal design; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Signal Processing, VI, 1993., [Workshop on]
Conference_Location :
Veldhoven
Print_ISBN :
0-7803-0996-0
Type :
conf
DOI :
10.1109/VLSISP.1993.404497
Filename :
404497
Link To Document :
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