Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in self- test (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present test cost reduction requirements and techniques from a circuit design perspective. One promising approach for the test of fully-integrated RF transceiver front-ends with on-chip loopback and strategically placed power detectors along the RF signal path will be discussed as a demonstrative example of the presented concepts. The main focus in this paper is on reported work that is relevant to improvement of test coverage and cost reduction for on-wafer functional test with minimal area overhead and test time.