A new approach to analyze interconnect delays in RC wire models

This paper studies the step-response of RC wires with source resistance R_S and load capacitance C_L, which is the most commonly used model for a wire in VLSI circuits. In particular, we obtain the normalized values of some of the common threshold-crossing times at the output load. Asymptotic waveform evaluation (AWE) is utilized to calculate time delay differences. Graphical aids to determine the required number of RC cells in an interconnect are proposed. The accuracy of the RC lumped circuit models are dependent not only on the number of sections, but also on the ratio of wire resistance to source resistance and on the ratio of wire capacitance to load capacitance. A kind of symmetry between T- and Pi-structure models is also illustrated in this paper