Title :
A new approach to analyze interconnect delays in RC wire models
Author :
Jin, Zhong-Fang ; Laurin, Jean-Jacques ; Savaria, Yvon ; Garon, Pierre
Author_Institution :
Ecole Polytech. de Montreal, Que., Canada
Abstract :
This paper studies the step-response of RC wires with source resistance RS and load capacitance CL, which is the most commonly used model for a wire in VLSI circuits. In particular, we obtain the normalized values of some of the common threshold-crossing times at the output load. Asymptotic waveform evaluation (AWE) is utilized to calculate time delay differences. Graphical aids to determine the required number of RC cells in an interconnect are proposed. The accuracy of the RC lumped circuit models are dependent not only on the number of sections, but also on the ratio of wire resistance to source resistance and on the ratio of wire capacitance to load capacitance. A kind of symmetry between T- and Pi-structure models is also illustrated in this paper
Keywords :
RC circuits; VLSI; capacitance; circuit simulation; delays; integrated circuit interconnections; integrated circuit modelling; lumped parameter networks; wiring; Pi-structure models; RC cells; RC wire models; T-structure models; VLSI circuits; asymptotic waveform evaluation; common threshold-crossing times; interconnect delays; load capacitance; lumped circuit models; normalized values; output load; source resistance; step-response; time delay differences; wire capacitance; wire resistance; Capacitance; Delay effects; Distributed parameter circuits; Integrated circuit interconnections; Integrated circuit modeling; Logic; Threshold voltage; Transmission line theory; Very large scale integration; Wire;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780141