An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles

In this paper, we present an automatic clock tree design (ACTD) system for high speed VLSI designs. The ACTD is designed to extend the capabilities of the existing computer aided design tools and provides a convenient environment for CAD users. Specifically, the following issues are considered: (i) a planar clock routing, (ii) a solution for avoiding obstacles, (iii) strategy of buffer insertion, and (iv) a complete system for clock routing. To achieve a planar clock routing, we first present a cutting-line embedding routing algorithm which constructs a planar clock tree topology. Then, we employ heuristic techniques called planar obstacle-avoiding routing which can solve the obstacle-crossing in the clock net. Therefore, this paper introduces two novel algorithms for developing a planar clock routing system with the treatment of obstacles. Both a cutting-line embedding algorithm and a planar obstacle-avoiding routing algorithm show a good enhancement in convenient usage and performance