New low-cost thermally stable process to reduce silicon substrate: a way to extreme frequencies for high volume Si technologies

Using a semi-insulating channel stopper (SICS) layer, silicon substrate RF losses have been eliminated on high resistive silicon wafers (HRS) up to 100 GHz, even after thermal treatments up to 1100°C. The integration of the SICS layer is demonstrated at the bottom of shallow trench isolation (STI) in a state-of-the-art CMOS technology. These results open a way to easily integrate low-cost high quality passive devices into standard high volume Si technologies.