A power driven two-level logic optimizer

Author

Tseng, Jyh-Mou ; Jou, Jing-Yang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1997

fDate

28-31 Jan 1997

Firstpage

113

Lastpage

116

Abstract

In this paper we present Boolean techniques for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates and dynamic PLA implementations. We modify Espresso algorithm by adding our heuristics that bias the logic minimization toward lowering the power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising

Keywords

Boolean functions; circuit optimisation; combinational circuits; logic CAD; minimisation of switching nets; multivalued logic circuits; power consumption; programmable logic arrays; Boolean techniques; Espresso algorithm; dynamic PLA implementations; general logic gates; logic minimization; low power targeting static PLA; power driven two-level logic optimizer; signal probabilities; transition densities; two-level combinational circuits; two-level logic optimizer; Capacitance; Combinational circuits; Cost function; Energy consumption; Minimization methods; Packaging; Power dissipation; Power engineering and energy; Probability; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

0-7803-3662-3

Type

conf

DOI

10.1109/ASPDAC.1997.600069

Filename

600069