Title :
DC parameterized piecewise-function transistor models for bipolar and MOS logic stage delay evaluation
Author :
Holberg, Douglas R. ; Dutta, Santanu ; Pillage, Lawrence
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
A novel technique is presented for analyzing nonlinear active devices driving RC trees which accounts for nonlinear behavior in such a way that the accuracy obtained is typically within 10% of SPICE. This is achieved with a tremendous savings in calculation time as compared to SPICE, using exclusively DC parameterized transistor models. These models have been included in a prototype program for analyzing bipolar and CMOS logic-stage delay models. These techniques are currently being extended to provide best-case and worst-case delay approximations in terms of the DC parameterized piecewise-linear and piecewise-quadratic Thevenin models.<>
Keywords :
CMOS integrated circuits; bipolar integrated circuits; circuit analysis computing; delays; integrated logic circuits; nonlinear network analysis; piecewise-linear techniques; semiconductor device models; CMOS logic-stage delay; DC parameterized; MOS logic; RC trees; Thevenin models; bipolar logic stage delay; delay approximations; nonlinear active devices; piecewise-function transistor models; piecewise-linear; piecewise-quadratic; transistor models; Circuit simulation; Delay; Integrated circuit interconnections; Load modeling; Logic circuits; Logic devices; MOSFETs; Predictive models; RLC circuits; Timing;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129977
