Fault-tolerant digital filtering structures for wafer scale VLSI

Digital filtering architectures that simultaneously offer advantages for wafer VLSI fabrication and contain distributed error-control are presented. Such structures require parallelism as well as inherent error-control capabilities because VLSI implementations are susceptible to temporary and intermittent hardware errors such as soft fails. Convolutions are implemented by finite field arithmetic subsections, where the operations in the various subsections are equivalent to polynomial multiplications, leading to the natural introduction of cyclic codes in the basic architecture. A polynomial expansion technique permits powerful cyclic subcodes to be introduced in each parallel subsection resulting from such a decomposition. Locations for error control within the architectures are examined, and several approaches for combatting failures are detailed.