Low contact resistance polysilicon plug for halfmicron CMOS technology

Author

Hamajima, Toshiki ; Sugano, Yukiyasu

Author_Institution

Sony Corp., Kanagawa, Japan

fYear

1989

fDate

12-13 Jun 1989

Firstpage

144

Lastpage

150

Abstract

A polycrystalline silicon (polysilicon) plug was developed for the planarization of high-aspect-ratio contact holes. Using this method, the authors realized a low contact resistance of 118 Ω on p-type and 57 Ω on n-type diffusion layers for 0.6-μm hole diameter and 0.8-μm hole depth. Moreover, a shallow source/drain junction of 0.15-μm depth using rapid thermal annealing (RTA) was obtained. The key issues in this technology are the double (low- and high-energy) ion implantation of boron for the p-type plug and low-temperature insertion and subsequent deposition of polysilicon and dopant activation by RTA in the plugs and diffused layers at the same time

Keywords

CMOS integrated circuits; contact resistance; incoherent light annealing; integrated circuit technology; ion implantation; 0.6 micron; 0.8 micron; 118 ohm; 57 ohm; CMOS technology; RTA; Si:B; contact resistance; high-aspect-ratio contact holes; hole depth; hole diameter; ion implantation; low-temperature insertion; n-type diffusion layers; planarization; polysilicon plug; rapid thermal annealing; shallow source/drain junction; CMOS technology; Conductivity; Contact resistance; Electrical resistance measurement; Etching; Inductors; Ion implantation; Planarization; Plugs; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1989.78017

Filename

78017