Title :
An approach to behavioral synthesis for loop-based BIST
Author :
Li, Xiaowei ; Cheung, Paul Y S
Author_Institution :
Dept. of Comput. Sci. & Technol., Peking Univ., Beijing, China
Abstract :
This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of the BIST scheme during behavioral synthesis processes, an area optimal BIST solution can be obtained. This approach is based on the use of rest resources reusability which results in a fewer number of registers being modified as BIST registers. This is achieved by incorporating testability constraints during register assignment operations. Experimental results on benchmarks are presented to demonstrate the effectiveness of the approach
Keywords :
built-in self test; integrated circuit design; logic design; shift registers; BIST registers; behavioral synthesis; benchmarks; effectiveness; loop-based BIST; optimal BIST; resources reusability; testability constraints; Benchmark testing; Built-in self-test; Circuit synthesis; Circuit testing; Computer science; Concurrent computing; Hardware; Minimization; Registers; Test pattern generators;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780173
