Title :
A non-zero clock skew scheduling algorithm for high speed clock distribution network
Author :
Maaz, Mohamad B. ; Bayoumi, Magdy A.
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
Abstract :
In this paper, we present a novel algorithm for scheduling clock skews in a synchronous digital circuits to optimize performance. The new algorithm is based on inclusively matching allowable clock skews intervals of all local data path in the circuit in order to determine the proper global skew ranges. This algorithm will lead to minimizing the clock period as well as obtaining a list of scheduled skews to be inserted in the clock network. These scheduled skews are then used to obtain a delay model for all branches of the clock distribution network tree. The delay values ensure the proper synchronization of data and eliminate any potential race condition in the circuit. The new algorithm has been tested and found to be a good approach toward reducing the clock period compared with zero intentional skew clocking
Keywords :
clocks; delays; distribution networks; high-speed integrated circuits; integrated circuit design; logic design; minimisation; scheduling; synchronisation; VLSI/ULSI; clock network; clock skews; high speed clock distribution network; inclusively matching allowable clock skews intervals; local data path; non-zero clock skew scheduling algorithm; scheduled skews; synchronization; synchronous digital circuits; zero intentional skew clocking; Circuit testing; Clocks; Computer networks; Delay; Digital circuits; Distributed computing; Frequency; High performance computing; RLC circuits; Scheduling algorithm;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780175
