A non-zero clock skew scheduling algorithm for high speed clock distribution network

In this paper, we present a novel algorithm for scheduling clock skews in a synchronous digital circuits to optimize performance. The new algorithm is based on inclusively matching allowable clock skews intervals of all local data path in the circuit in order to determine the proper global skew ranges. This algorithm will lead to minimizing the clock period as well as obtaining a list of scheduled skews to be inserted in the clock network. These scheduled skews are then used to obtain a delay model for all branches of the clock distribution network tree. The delay values ensure the proper synchronization of data and eliminate any potential race condition in the circuit. The new algorithm has been tested and found to be a good approach toward reducing the clock period compared with zero intentional skew clocking