Title :
A constraint-based placement refinement method for CMOS analog cell layout
Author :
Zeng, X. ; Guan, J. ; Zhao, W.Q. ; Tang, P.S. ; Zhou, D.
Author_Institution :
Dept. of Electr. Eng., Fudan Univ., Shanghai, China
Abstract :
The performance of analog circuits is sensitive to fabrication process and the layout of their physical masks. In this paper, a novel constraint-based methodology is proposed for the placement refinement of CMOS analog cell circuits. Constraint-based module generation and shaping process are also developed not only to optimize the layout shape, area but more importantly to guarantee the analog circuits performance. A hybrid-tree model is proposed to simultaneously represent the geometry, symmetry and parasitic constraints for the layout. Experimental results have shown the effectiveness of the proposed method
Keywords :
CMOS analogue integrated circuits; circuit CAD; circuit optimisation; integrated circuit layout; network routing; CMOS analog cell layout; analog circuits; constraint-based methodology; constraint-based placement refinement; effectiveness; fabrication; geometry; hybrid-tree model; layout; parasitic constraints; placement refinement; symmetry; Analog circuits; CMOS analog integrated circuits; Constraint optimization; Geometry; MOSFETs; Parasitic capacitance; Semiconductor device modeling; Shape control; Simulated annealing; Solid modeling;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780181
