A New Method for FPGA-Based 24x24-Bit Low-Power Multiplier

Through improving the existing coding algorithms, this paper presents a new coding algorithm, which reduces power dissipation in the way of reducing the number of partial product. Because the main operation of the multiplier is the sum of partial products, therefore, the reduction of the number of partial product can decrease the number of adder in multiplier, so the power dissipation can be decreased. The multiplier was given the results of simulation and test, and was compared with the multipliers which were designed with the existing coding algorithms, and the power dissipation was decreased by 3.5% and 8.4%.