• DocumentCode
    3002183
  • Title

    Equivalence classes of clone circuits for physical-design benchmarking

  • Author

    Hutton, Michael D. ; Rose, Jonathan

  • Author_Institution
    Altera Corp., San Jose, CA, USA
  • Volume
    6
  • fYear
    1999
  • fDate
    36342
  • Firstpage
    428
  • Abstract
    To provide a better understanding of physical design algorithms and the underlying circuit architecture they are targeting, we need to exercise the algorithms and architectures with many benchmark circuits. The lack of existing benchmarks makes us consider the automatic generation of netlists. In this paper, we formally define the equivalence class of circuit “clones” of a given seed circuits, based upon physical properties of the seed circuit´s netlist graph. Using these equivalence classes of circuits, a given seed circuit can be used to generate many similar circuits. A more finely grained statistical analysis of algorithm behaviour can then be obtained from using the multiple benchmarks than would be available from using the seed benchmark alone
  • Keywords
    equivalence classes; graph theory; network synthesis; automatic generation; benchmark circuit; circuit architecture; clone circuit; equivalence class; netlist graph; physical design algorithm; seed circuit; statistical analysis; Application specific integrated circuits; Benchmark testing; Circuit testing; Cloning; Logic design; Logic gates; Routing; Statistical analysis; Table lookup; Technological innovation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    0-7803-5471-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1999.780186
  • Filename
    780186