Title :
Design and process integration for high-density, high-speed, and low-power 6F2 cross point MRAM cell
Author :
Asao, Yoshiaki ; Amano, M. ; Aikawa, H. ; Ueda, T. ; Kishi, T. ; Ikegawa, S. ; Tsuchida, K. ; Yoda, H. ; Kajiyama, T. ; Fukuzumi, Y. ; Iwata, Y. ; Nitayama, A. ; Shimura, K. ; Kato, Y. ; Miura, S. ; Ishiwata, N. ; Hada, H. ; Tahara, S.
Author_Institution :
Corporate R&D Center, Toshiba Corp., Kanagawa, Japan
Abstract :
A cross point (CP) cell with hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) based in Y. Shimizu et al. (2004). The new CP cell has a potential high density of 6F2 and a faster access time than the conventional CP cell. A cell layout design to realize 6F is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 μm CMOS technology and 0.24×0.48 μm2 magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.
Keywords :
CMOS memory circuits; integrated circuit design; low-power electronics; magnetic tunnelling; magnetoresistive devices; random-access storage; 0.13 micron; 1 Mbit; 1.5 V; 250 ns; CMOS technology; MRAM chip; cell layout; cross point MRAM cell; faster access time; hierarchical bit line; high-density MRAM; high-speed MRAM; low-power MRAM; magnetic tunnel junction; magnetoresistive random access memory; process integration; yoke wires; CMOS process; CMOS technology; Contact resistance; Magnetic tunneling; Magnetostriction; Process design; Random access memory; Switches; Wires; Writing;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419224
