DocumentCode :
3002291
Title :
Applications of clone circuits to issues in physical-design
Author :
Hutton, Michael D. ; Rose, Jonathan
Author_Institution :
Altera Corp., San Jose, CA, USA
Volume :
6
fYear :
1999
fDate :
36342
Firstpage :
448
Abstract :
In a companion paper of this session we formally defined the notion of equivalence classes of circuits which are physical clones of an existing benchmark seed circuit created by the GEN tool. Here we use well-known partitioning and placement tools to study the behaviour of clone circuits. We outline a simple methodology for using equivalence classes of clone circuits for benchmarking. We then apply the methodology to the example of netlist partitioning by generating a large set of clones of a starting benchmark set in order to statistically distinguish two netlist partitioning algorithms. The primary purpose of this paper is to outline the acceptable and valid uses of clone circuits for benchmarking. In addition to specific examples we will also discuss practical experience with circuits produced by the current version of GEN, so that the user is aware of for what purposes GEN is currently useful, and for what purposes user aid or further research is required
Keywords :
circuit layout CAD; integrated circuit layout; logic CAD; logic partitioning; sequential circuits; GEN tool; benchmark seed circuit; clone circuits; equivalence classes; netlist partitioning; partitioning algorithms; physical-design; placement tools; Analysis of variance; Application software; Circuit testing; Cloning; Educational institutions; Partitioning algorithms; Physical layer; Sequential circuits; Table lookup; Technological innovation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
Type :
conf
DOI :
10.1109/ISCAS.1999.780191
Filename :
780191
Link To Document :
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