• DocumentCode
    3002323
  • Title

    An improved fault tolerant architecture at CMOS level

  • Author

    Bolchini, C. ; Buonanno, G. ; Sciuto, D. ; Stefanelli, R.

  • Author_Institution
    Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
  • Volume
    4
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    2737
  • Abstract
    A previous realization of a fault tolerant architecture at CMOS level, while guaranteeing the correct behavior of the circuit both in the fault-free situation and in the presence of stuck-on faults, was characterized by a neither null nor +Vdd output voltage when faults occurred. An improved architecture is here presented, which by adding additional transistors, achieves the fault tolerance property without degrading the performance of the circuit in terms of output voltage and short circuit current
  • Keywords
    CMOS integrated circuits; integrated circuit design; CMOS circuit; fault tolerant architecture; output voltage; short circuit current; stuck-on fault; transistor; CMOS technology; Circuit faults; Degradation; Delay; Design methodology; Electronic mail; Fault diagnosis; Fault tolerance; Semiconductor device modeling; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.612891
  • Filename
    612891
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3002323