DocumentCode
3002332
Title
Cost-effective co-verification using RTL-accurate C models
Author
Jain, Prem P.
Author_Institution
CAE Plus Inc., Austin, TX, USA
Volume
6
fYear
1999
fDate
36342
Firstpage
460
Abstract
The verification quality of a system on chip (SOC) design depends on the number of simulations that can be performed under time-to-market constraints. This in turn depends on both the simulation speed and the cost of multiple simulator licenses. Since HDL simulators are both slow and expensive, design quality suffers. This paper presents a methodology and associated tools for the use of RTL-accurate C models for fast and cost-effective verification
Keywords
C language; VLSI; circuit simulation; digital simulation; formal verification; integrated circuit design; logic CAD; RTL-accurate C models; co-verification; cost-effective verification; multiple simulator licenses; simulation speed; system on chip design; time-to-market constraints; verification quality; Computational modeling; Computer aided engineering; Cost function; Hardware design languages; Licenses; Protection; Software performance; System-on-a-chip; Time to market; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.780194
Filename
780194
Link To Document