Co-verification as risk management: minimizing the risk of incorporating a new processor in your next embedded system design

According to EE-Times over 60% of current 8-bit and 16-bit users are considering moving to 32-bit embedded controllers. However, many development teams are not able to accurately assess the impact to the project schedule of adopting a new processor. New busses, peripherals and a more complex initialization sequence increase the project risk, especially when few engineers on the team have experience with the new target. Hardware/Software Co-Verification is a proven method for reducing the risk associated with introducing a new CPU into the project. This paper will discuss the features and limitations of co-verification as well as detail some customer experiences. The type of software that is practical to execute using co-verification and specific customer design errors exposed will be presented