FFT implementation on the TMS320C30

Author

Papamichalis, Panos E.

Author_Institution

Texas Instrum. Inc., Houston, TX, USA

fYear

1988

fDate

11-14 Apr 1988

Firstpage

1399

Abstract

The implementation of several FFT (fast Fourier transform) algorithms on the TMS320C30, the third-generation device in the Texas Instruments family of digital signal processors is reported. The algorithms considered are the complex radix-2 and radix-4, and real-valued radix-2 FFT. The architecture and the instruction set of the TMS320C30 permit flexible and compact coding of the algorithms in assembly language while preserving close correspondence to a high-level language implementation. The efficiency of the architecture and the speed of the device (60 ns) make possible the realization of a 1024-point FFT in 3.75 ms (complex, radix-2), 3.04 ms (complex, radix-4), or 1.67 ms (real, radix-2)

Keywords

fast Fourier transforms; signal processing; 1.67 ms; 3.04 ms; 3.75 ms; FFT algorithms; TMS320C30; Texas Instruments; architecture; assembly language; coding; complex radix-2; complex radix-4; digital signal processors; fast Fourier transform; high-level language implementation; instruction set; real-valued radix-2 FFT; Digital signal processing; Fast Fourier transforms; Floating-point arithmetic; Hardware; High level languages; Instruments; Pipelines; Signal generators; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on

Conference_Location

New York, NY

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1988.196860

Filename

196860