DocumentCode
3002517
Title
A high speed CMOS/SOS implementation of a bit level systolic correlator
Author
White, J.C. ; McCanny, J.V. ; McCabe, A. ; McWhirter, J. ; Evans, R.
Author_Institution
Marconi Electronic Devices, Lincoln
Volume
11
fYear
1986
fDate
31503
Firstpage
1161
Lastpage
1164
Abstract
The fabrication and performance of the first bit level systolic correlator array is described. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64 stage correlation for 1 bit reference and 4 bit data.
Keywords
Adders; Circuits; Computer architecture; Correlators; Fabrication; Matrix decomposition; Pipelines; Signal processing; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
Type
conf
DOI
10.1109/ICASSP.1986.1168833
Filename
1168833
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