Hardware implementation of a nonlinear processor

Several advanced DSP algorithms, arising in applications such as wireless communications, computer graphics, computerized tomography, and speech compression, require extensive use of nonlinear functions. We discuss a new hardware approach to high-speed computation of nonlinear functions. With this approach all of the functions needed can be regularized into a single efficient algorithm. Further, highly reduced cycle implementations can be achieved. Specifically, for real arguments, a new result can be produced every cycle-in a pipelined mode. The underlying principle which has made the combined goals of high-speed and multi-functionality possible is significance-based polynomial interpolation of very small ROM tables. Considered are the following seven functions: arctangent, cosine, logarithm, reciprocal, reciprocal-square-root, sine, and square-root. Also presented is a theoretical development for error prediction, a tool for the selection of architectural parameters. Finally, the paper presents a novel technique, named here as `microshaping´, for avoiding overflows, thereby eliminating exception handling