Title :
Multi-level logic optimization for large scale ASICs
Author :
Nagoya, Akira ; Nakamura, Yukihiro ; Oguri, Kiyoshi ; Nomura, Ryo
Author_Institution :
NTT Commun. & Inf. Process. Lab., Kanagawa, Japan
Abstract :
The authors developed an efficient high-level synthesis and optimization system for large-scale circuits, which reduces the total number of fan-ins in the technology-independent phase and adjusts speed and area after technology mapping is completed. A description is presented of multi-level logic optimization techniques based on refined weak division methods and additional functions for carrying out good optimization with only a slight overhead. The authors also describe technology mapping and local optimization techniques suitable for high-level CAD systems. The system has shown that multi-level logic optimization in VLSIs with more than 100000 gates (that is, VLSIs whose control logic comprises more than 10000 gate circuits) is possible in practical CPU time.<>
Keywords :
application specific integrated circuits; circuit CAD; integrated logic circuits; logic CAD; fan-ins; large scale ASICs; logic optimization; multi-level logic; refined weak division; technology mapping; Application specific integrated circuits; Central Processing Unit; Circuit synthesis; Control system synthesis; Design automation; Hardware; Large-scale systems; Logic circuits; Logic design; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129982