DocumentCode
3002575
Title
Pragmatic design of nanoscale multi-gate CMOS
Author
Fossum, J.G. ; Wang, L.Q. ; Yang, J.W. ; Kim, S.H. ; Trivedi, V.P.
Author_Institution
Florida Univ., Gainesville, FL, USA
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
613
Lastpage
616
Abstract
Three-dimensional numerical device simulations are done to gain physical insights on multi-gate FinFETs, which portend the infeasibility of nanoscale triple-gate CMOS, and process/physics-based device/circuit simulations are done to check the concept of pragmatic nanoscale double-gate CMOS design, showing encouraging performance projections near the end of the SIA 2003 ITRS (2003).
Keywords
CMOS integrated circuits; circuit simulation; field effect transistors; integrated circuit design; nanoelectronics; semiconductor device models; 3D numerical device simulation; multigate FinFET; nanoscale multigate CMOS; nanoscale triple-gate CMOS; physics-based simulation; pragmatic nanoscale double-gate CMOS design; process-based simulation; CMOS process; Current-voltage characteristics; Doping; FinFETs; MOSFET circuits; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN
0-7803-8684-1
Type
conf
DOI
10.1109/IEDM.2004.1419236
Filename
1419236
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