Title :
Design and implementation of MIC@R router for on-chip networks
Author :
Ben-Tekaya, Rafik ; Baganne, Adel ; Torki, Kholdoun ; Tourki, Rached
Author_Institution :
Fac. of Sci. at Monastir, Electron. & Micro-Electron. Lab., Monastir
Abstract :
The paper presents a design and implementation of router architecture suitable for Networks-on-Chip (NoC) design. This architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using Fast Parallel Routing (FPR) arbitration that consists in parallel processing and in one stage the routing decisions and arbitration. The proposed router architecture is implemented in ASIC technology and evaluated in 2D Mesh networks with three adaptive routing algorithms: Fully Adaptive (FA), Proximity Congestion Awareness (PCA) and Contention Look-Ahead (CLA). The obtained results show that our router, combined with adaptive routing techniques is effective in terms of latency and throughput.
Keywords :
application specific integrated circuits; network routing; network-on-chip; parallel processing; 2D Mesh networks; ASIC technology; NoC design; adaptive routing algorithms; contention look-ahead algorithms; fast parallel routing; fully adaptive algorithms; networks-on-chip; on-chip networks; parallel processing; proximity congestion awareness algorithms; router architecture; routing latency; Application specific integrated circuits; Buffer storage; Communication system control; Delay; Network-on-a-chip; Principal component analysis; Routing; System recovery; Throughput; Virtual colonoscopy;
Conference_Titel :
Design and Test Workshop, 2008. IDT 2008. 3rd International
Conference_Location :
Monastir
Print_ISBN :
978-1-4244-3479-4
Electronic_ISBN :
978-1-4244-3478-7
DOI :
10.1109/IDT.2008.4802457
