DocumentCode :
3002668
Title :
High speed signal processing, pipelining, and VLSI
Author :
Hatamian, Mehdi ; Cash, Glenn L.
Author_Institution :
AT&T Bell Laboratories, Holmdel, NJ, USA
Volume :
11
fYear :
1986
fDate :
31503
Firstpage :
1173
Lastpage :
1176
Abstract :
In this paper we discuss issues arising in the design of highly pipelined VLSI circuits for high-speed signal processing applications. Problems such as clock skew, buffer design, clock distribution network, and timing simulation are addressed, and methods of alleviating them are presented. The impact of technology on the degree of pipelining is discussed. Some design examples, including an 8-bit systolic multiplier fabricated in 2.5 micron CMOS technology and tested up to 70 MHz multiplication rate, are presented. The extension of this design to a systolic multiply-add/accumulate chip and its applications are briefly discussed.
Keywords :
CMOS technology; Circuits; Clocks; Pipeline processing; Registers; Signal processing; Signal processing algorithms; Testing; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.
Type :
conf
DOI :
10.1109/ICASSP.1986.1168842
Filename :
1168842
Link To Document :
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