A parallel architecture for recursive least square identification

In this paper, we propose a parallel architecture for computing recursive least square (RLS) identification, designed for VLSI. The RLS identification is the most fundamental method of estimating system parameters and is widely used in various fields of signal processing and control. The main bottleneck of its on-line use is its computational complexity which requires O(n²) unit times at each step of updating the estimate of system of O(n). Our architecture, composed of (2n+6) elementaly processors and a bank of delay units, computes each step of updating in O(n) unit times. A method of enhancing the throughput by vectorizing the measurements is also given.