DocumentCode
3002758
Title
Universal test set for bridging fault detection in reversible circuit
Author
Sarkar, Pradyut ; Chakrabarti, Susanta
Author_Institution
Dept. of Res. & Dev. of VLSI Technol., Simplex Infrastruct. Ltd., Kolkata
fYear
2008
fDate
20-22 Dec. 2008
Firstpage
51
Lastpage
56
Abstract
Detection of bridging faults plays a significant role in a reversible circuit. The single and multiple inputs bridging faults model of a reversible circuit is considered here. The paper proposes that only n (number of inputs) number of universal test vectors are sufficient for detection of all single and multiple input bridging faults and all input stuck-at faults of any n-input and n-output reversible circuit. A polynomial time algorithm is proposed for generating the universal test vectors for detecting of all single and multiple input bridging faults of the reversible circuit. The results on reversible benchmark circuit show that the number of universal test vectors are significantly reduced compared to the earlier works of reversible circuit and classical circuit.
Keywords
circuit reliability; circuit testing; fault diagnosis; logic circuits; logic testing; polynomial approximation; bridging faults; fault detection; reversible circuit; stuck-at faults; universal test set; Benchmark testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic circuits; Optical computing; Polynomials; Quantum computing; Very large scale integration; Complete test set; Reversible Gate; Single and multiple input bridging faults; Universal test set;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Test Workshop, 2008. IDT 2008. 3rd International
Conference_Location
Monastir
Print_ISBN
978-1-4244-3479-4
Electronic_ISBN
978-1-4244-3478-7
Type
conf
DOI
10.1109/IDT.2008.4802464
Filename
4802464
Link To Document