A regular representation for mapping to fine-grain, locally-connected FPGAs

Author

Chrzanowska-Jeske, Malgorzata ; Wang, Zhi ; Xu, Yang

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

Volume

4

fYear

1997

fDate

9-12 Jun 1997

Firstpage

2749

Abstract

A new data structure Pseudo-Symmetric Binary Decision Diagrams (PSBDDs) for completely specified Boolean functions has been proposed. The new diagrams are based on Ordered Binary Decision Diagrams and contact symmetric networks. The main advantages of the PSBBDs are the regular structure and predictable delay of the interconnects. These structures are especially well suited for mapping to fine-grain, locally-connected FPGAs where a very restricted routing domain limits circuit performance, for and submicron technologies

Keywords

Boolean functions; directed graphs; field programmable gate arrays; logic design; Boolean function; PSBDD; circuit routing; contact symmetric network; data structure; fine-grain locally-connected FPGA; interconnect delay; mapping; ordered binary decision diagram; pseudo-symmetric binary decision diagram; submicron technology; Binary decision diagrams; Boolean functions; Circuit optimization; Circuit synthesis; Data structures; Delay; Field programmable gate arrays; Logic arrays; Routing; Terminology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.612894

Filename

612894