• DocumentCode
    3003029
  • Title

    A 65 nm CMOS technology for mobile and digital signal processing applications

  • Author

    Chatterjee, A. ; Yoon, J. ; Zhao, S. ; Tang, S. ; Sadra, K. ; Crank, S. ; Mogu, H. ; Aggarwa, R. ; Chatterjee, B. ; Lytle, S. ; Lin, C.T. ; Lee, K.D. ; Kim, J. ; Hong, Q.Z. ; Kim, T. ; Olsen, L. ; Quevedo-Lopez, M. ; Kirmse, K. ; Zhang, G. ; Meek, C. ; Al

  • Author_Institution
    SiTD, Texas Instruments Inc., Dallas, TX, USA
  • fYear
    2004
  • fDate
    13-15 Dec. 2004
  • Firstpage
    665
  • Lastpage
    668
  • Abstract
    This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/mm2 and a SRAM memory density of 1.4 Mb/mm2 using a sub-0.49 μm2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.
  • Keywords
    CMOS logic circuits; SRAM chips; digital signal processing chips; mobile communication; nanoelectronics; 65 nm; CMOS technology; SRAM memory density; digital signal processing; high performance technology; logic density; mobile applications; mobile products; CMOS logic circuits; CMOS process; CMOS technology; Costs; Digital signal processing; Energy management; Isolation technology; MOS devices; Random access memory; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
  • Print_ISBN
    0-7803-8684-1
  • Type

    conf

  • DOI
    10.1109/IEDM.2004.1419255
  • Filename
    1419255
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3003029