DocumentCode
3003078
Title
Notice of Retraction
High speed asynchronous ADC in CAD mentor graphics AMS 0,35 µm CMOS
Author
Purnomo, J. ; Afandi, H. ; Prasetyo, E.
Author_Institution
Gunadarma Univ., Depok, Indonesia
fYear
2010
fDate
11-12 June 2010
Firstpage
406
Lastpage
409
Abstract
Notice of Retraction
After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.
We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.
The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.
This paper contains the asynchronous ADC design specification which has high speed and low power. Asynchronous ADC consists of 3 blocks of units composer OPAMP, Digital Logic and Switch Capacitor. Needs high-speed ADC is needed to convert analog signals to digital which is applied to a multimedia device, especially for video signal applications. Low power consumption is useful for efficient power use. The method used in the design is an experiment with simulation CAD software mentor graphics technology with technology CMOS of AMS (Austria Micro Systems) 0.35 μm. Stage design is the A-ADC circuit design with simulation results. The end result is to obtain a design prototype A-3-bits ADC, power consumption <;15mW and voltage 3.3 V. CT.
After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.
We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.
The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.
This paper contains the asynchronous ADC design specification which has high speed and low power. Asynchronous ADC consists of 3 blocks of units composer OPAMP, Digital Logic and Switch Capacitor. Needs high-speed ADC is needed to convert analog signals to digital which is applied to a multimedia device, especially for video signal applications. Low power consumption is useful for efficient power use. The method used in the design is an experiment with simulation CAD software mentor graphics technology with technology CMOS of AMS (Austria Micro Systems) 0.35 μm. Stage design is the A-ADC circuit design with simulation results. The end result is to obtain a design prototype A-3-bits ADC, power consumption <;15mW and voltage 3.3 V. CT.
Keywords
circuit CAD; logic design; A-ADC circuit design; AMS 0.35 μm CMOS; Austria Micro Systems; asynchronous ADC design specification; design prototype A-3-bits ADC; digital logic; high speed asynchronous ADC; multimedia device; simulation CAD software mentor graphics technology; switch capacitor; video signal applications; Application software; CMOS logic circuits; CMOS technology; Capacitors; Circuit simulation; Design automation; Energy consumption; Graphics; Logic devices; Switches; ADC; Analog; DAC; Digital Logic; Op-Amp; data; digital;
fLanguage
English
Publisher
ieee
Conference_Titel
Networking and Information Technology (ICNIT), 2010 International Conference on
Conference_Location
Manila
Print_ISBN
978-1-4244-7579-7
Type
conf
DOI
10.1109/ICNIT.2010.5508483
Filename
5508483
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