Low power design of on-line testers for digital circuits using state encoding

This work is concerned with the development of an algorithm for lowering the power consumption of the tester used in digital circuits with on line testing (OLT) capability by encoding the states of the on-line tester. Most of the work presented in the literature on OLT have emphasized on minimizing area overhead maintaining high fault coverage. However, power, which was mainly a concern for handheld devices, is now a first order impact factor for deep submicron designs. Its increased importance for OLT can be realized from the fact that the tester is executed concurrently with the circuit. The proposed technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal impact on performance in terms of area overhead the proposed technique can lower the power significantly, compared to traditional approaches.