An ultra high speed low-power CMOS integrated current comparator

This paper presents an ultra high speed low current comparator with low input impedance using a simple biasing method. It is optimized for low power consumption whilst maintaining high speed. This novel comparator design offers a reduction in power consumption compared with other high speed designs. Simulation results demonstrate the propagation delay is about 0.7 nsec and the average power consumption is 107 muW for 100 nA input current at supply voltage of 1.8 V using 0.35 mum CMOS technology.