An efficient hardware architecture design for H.264/AVC INTRA 4×4 algorithm

In this work, we present architecture for real-time implementation of INTRA 4X4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4times4 is composed by intra prediction 4times4, integer transform 4times4, quantization 4times4, inverse integer transform 4times4, inverse quantization 4times4. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles.