Efficient FPGA prototyping of fixed sphere decoder for MIMO systems

Author

Khairy, Mohamed S. ; Abdallah, Mohamed M. ; Habib, S. E -D

Author_Institution

Electron. & Commun. Dept., Cairo Univ., Giza

fYear

2008

fDate

20-22 Dec. 2008

Firstpage

177

Lastpage

181

Abstract

In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4times4 MIMO systems using 16-QAM modulation scheme.

Keywords

MIMO communication; decoding; field programmable gate arrays; matrix algebra; quadrature amplitude modulation; 16-QAM modulation scheme; FPGA prototyping; MIMO systems; Matlab simulation model; channel matrix; multiple input multiple-output technology; of fixed sphere decoder; Detectors; Field programmable gate arrays; Hardware; MIMO; Mathematical model; Maximum likelihood decoding; Prototypes; Receiving antennas; Throughput; Transmitting antennas; FPGA Prototyping; MIMO Systems; Sphere Decoder; Wireless Communications;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Workshop, 2008. IDT 2008. 3rd International

Conference_Location

Monastir

Print_ISBN

978-1-4244-3479-4

Electronic_ISBN

978-1-4244-3478-7

Type

conf

DOI

10.1109/IDT.2008.4802492

Filename

4802492