Efficient FPGA prototyping of fixed sphere decoder for MIMO systems

In this paper, we present a FPGA prototyping of a fixed sphere MIMO decoder as well as a QR implementation of the channel matrix. The FPGA implementation is incorporated with a Matlab simulation model of the MIMO system to validate the hardware design. The proposed design compares favorably to published FPGA implementations of the fixed sphere MIMO decoders, with respect to both the hardware area and throughput metrics. The presented FPGA prototype of the FSD achieves a fixed throughput of 800 Mbps for 4times4 MIMO systems using 16-QAM modulation scheme.