Title :
A 13.3ns double-precision floating-point ALU and multiplier
Author :
Yamada, H. ; Hotta, T. ; Nishiyama, T. ; Murabayashi, F. ; Yamauchi, T. ; Sawamoto, H.
Author_Institution :
Res. Lab., Hitachi Ltd., Kanagawa, Japan
Abstract :
One-bit pre-shifting before alignment shift, normalization with anticipated leading `1´ bit and pre-rounding techniques have been developed for a floating-point arithmetic logic unit (ALU). In addition, carry select addition and pre-rounding techniques have been developed for a floating-point multiplier. A noise tolerant precharge (NTP) circuit was designed and applied to the ALU and multiplier. These techniques reduced the delay time of the critical path by 24%. Each unit was fabricated in 0.3 μm 2.5 V four-layer-metal CMOS technology and achieved a two-cycle latency at 150 MHz
Keywords :
CMOS integrated circuits; floating point arithmetic; multiplying circuits; 0.3 micron; 13.3 ns; 150 MHz; 2.5 V; CMOS technology; arithmetic logic unit; carry select addition; double-precision floating-point ALU; floating-point multiplier; noise tolerant precharge circuit; normalization; prerounding techniques; two-cycle latency; CMOS technology; Circuit noise; Cities and towns; Delay effects; Floating-point arithmetic; Laboratories; Logic; Silicon;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-7165-3
DOI :
10.1109/ICCD.1995.528909
