Title :
Efficient tests and DFT for RAM address decoder delay faults
Author :
Hamdioui, Said ; Al-Ars, Zaid
Author_Institution :
Comput. Eng. Lab., Delft Univ. of Technol., Delft
Abstract :
This paper presents an analysis, at the electrical level, of address decoder faults caused by resistive opens within (a) dynamic address decoders and (b) static address decoders, which have special circuits that deactivate them at fixed moment. Efficient algorithms are proposed to cover the targeted faults. DFT circuit, to facilitate the BIST implementation of the proposed tests, is also provided. Furthermore, the limitations of the current/existing approaches in detecting delay faults are addressed.
Keywords :
built-in self test; circuit testing; discrete Fourier transforms; random-access storage; BIST implementation; DFT; RAM address decoder delay faults; decoder faults; delay fault detection; dynamic address decoders; electrical level; static address decoders; Added delay; Circuit faults; Circuit testing; Decoding; Delay effects; Electrical fault detection; Fault detection; Random access memory; Read-write memory; System testing; Dynamic address decoders; delay faults; memory testing; open defects;
Conference_Titel :
Design and Test Workshop, 2008. IDT 2008. 3rd International
Conference_Location :
Monastir
Print_ISBN :
978-1-4244-3479-4
Electronic_ISBN :
978-1-4244-3478-7
DOI :
10.1109/IDT.2008.4802502
