Evaluation of SRAM faulty behavior under bit line coupling

The faulty behavior of memory devices has traditionally been evaluated in isolation of the parasitic effects present on chip. As these effects become more dominant, however, they start to negatively influence the fault coverage of commonly used memory tests. This paper studies the way bit line coupling affects the faulty behavior of SRAM devices. Spice simulations are used to show how coupling can prevent the detection of otherwise detectable faults. Furthermore, an evaluation is done of the needed bit line coupling conditions to guarantee a high fault coverage of a given defect. This is done by identifying the most stressful data background patterns in the neighborhood of the faulty cell.