A new cell-based performance metric for novel CMOS device architectures

This paper introduces, for the first time, a method for assessing the impact of CMOS technology choices on dynamic system level performance. The method is applied to the evaluation of five different device architectures, which include bulk, FDSOI, and multi-gate devices. Timing and power information at the standard cell level is extracted for each of the devices and used to simulate their performance embedded within a cell array of 230,400 cells.