Generation of test programs for the assertion-based verification of TLM models

The context of this paper is the dynamic ABV (assertion-based verification) of TLM (Transaction Level Modeling) SystemC specifications, which characterize SoCs at a very high level of abstraction. We use a framework for supervising during the SystemC simulation the verification of temporal properties expressed in the PSL language. The efficiency of this approach can be improved by the selection of well-chosen stimuli that enable the analysis of a range of nominal behaviors as well as of corner cases. To that goal, the simulation/monitoring environment is coupled with the combinatorial testing tool Tobias that builds on the experience of the test engineer captured in test patterns to define sets of interesting test cases.