Adaptive universal fault tolerant cellular logic arrays

This paper presents adaptive universal fault-tolerant logic arrays which have cellular structures, low numbers of input-output terminals, and are thus compatible with large scale integration technology. These cellular arrays can implement fault-tolerant digital systems capable of adapting on-line to realize any logic function on a given number of variables. The same simple adaptation algorithm employed to realize either a completely specified or an incompletely specified logic function is also used for dynamic error correction (on-line repair). The adaptive fault-tolerant cellular arrays are based on a proposed redundant decomposition of a switching function. A two-rail scheme of such arrays is shown to be capable of both error detection and dynamic error correction through adaptation. A comparison is carried out, which indicates that the reliability of the two-rail scheme is better than that of TMR schemes, for a comparable cost in hardware.