High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels

Author

Wu, Yung-Chun ; Chang, Chun-Yen ; Chang, Ting-Chang ; Liu, Po-Tsun ; Chen, Chi-Shen ; Tu, Chun-Hao ; Zan, Hsiao-Wen ; Tai, Ya-Hsiang ; Sze, Simon Min

Author_Institution

Inst. of Electron., National ChiaoTung Univ., Hsinchu, Taiwan

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

777

Lastpage

780

Abstract

We have investigated the lightly-doped drain (LDD) polysilicon thin-film transistors (poly-Si TFTs) with a series of multi-channel with different widths. The ten 67 nm-wide split channels TFT has best gate control due to its tri-gate structure, and has lowest poly-Si grain boundary defects, which were passivated by NH₃ plasma effectively due to its split nano-wires structure. The proposed TFT exhibits high performance electrical characteristics, such as a high ON/OFF current ratio (> 10⁹), a steep subthreshold slope (55) of 137 mV/decade, an absence of drain-induced barrier lowering (DIBL), suppressed kink-effect, and superior reliability.

Keywords

elemental semiconductors; grain boundaries; nanowires; semiconductor device manufacture; semiconductor device reliability; silicon; thin film transistors; 67 nm; ON/OFF current ratio; Si; drain-induced barrier lowering; gate control; high performance electrical characteristics; kink-effect supression; lightly-doped drain poly-Si TFT; multiple nanowire channels; plasma passivation; poly-Si grain boundary defects; polysilicon thin-film transistors; split channels TFT; split nanowires structure; subthreshold slope; tri-gate structure; CMOS technology; Electric variables; Electrodes; Etching; Leakage current; MOSFET circuits; Physics; Strips; Thin film transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419289

Filename

1419289