Reconfigurable pipeline for fast, versatile computation

To achieve maximum performance for actual algorithms, a computer system must provide more than raw throughput. Real-time signal processing and large-scale scientific computing require computational flexibility and high I/O bandwidth as well as peak MFLOPs (millions of floating-point operations per second) figures. A matrix signal processor is reported which combines the speed of a dedicated pipeline with the generality provided by a reconfigurable processor-interconnection network. High-volume data flow to the processor is maintained by a fast and wide data bus which joins processing modules and interface modules too form a complete signal processing system