Improved accuracy for logarithmic addition in DSP applications

Logarithmic number systems are an attractive method of implementing high-speed digital signal-processing systems with a word size of about 14 bits. Larger word sizes pose problems because of the address limitations of the ROMs needed for logarithmic addition. M.G. Arnold (1982) gave several interpolation techniques that can double the precision, but these techniques require the use of a fixed-point multiplier. F.J. Taylor (1983) proposed a modified linear interpolation that could increase the precision by about four bits without using a multiplier. It is shown that an improvement can be made in Taylor´s technique by choosing a different constant. Also, by combining one of Arnold´s techniques with a variant of Taylor´s modification, precision similar to that of Taylor´s design can be obtained using a simpler circuit