Title :
Copper as the future interconnection material
Author :
Pai, Pei-Lin ; Ting, Chiu H.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Cu film was evaluated as a candidate for future interconnection. As the device dimensions are scaled below 0.5 μm, the RC time constant of interconnection becomes a major part of the total delay. By reducing the resistivity of interconnect, the operating speed can be increased by more than 20% without any change in design rule. An electroless deposition process is proposed to solve the Cu patterning difficulty. Patterns of 2.0-μm pitch were achieved with this process. Copper contamination was addressed, and dielectric films such as silicon oxynitride and silicon nitride were shown to be effective in stopping Cu diffusion. The authors also investigated Cu corrosion. By coating a thin Ni film on Cu they reduced the corrosion from 0.2 μm/h to less than 0.05 μm/h at 100°C in 1-mol/1 KCl solution
Keywords :
VLSI; copper; corrosion; dielectric thin films; electroless deposition; integrated circuit technology; metallisation; nickel; silicon compounds; 0.5 micron; 100 C; 2 micron; Cu corrosion; Cu film; Cu patterning; KCl solution; KCl-H2O; Ni-Cu; RC time constant; Si3N4 film; SixOyNz film; VLSI; contamination; dielectric films; electroless deposition process; interconnection material; multilevel interconnection; operating speed; resistivity of interconnect; stopping Cu diffusion; thin Ni film; Coatings; Conductivity; Contamination; Copper; Corrosion; Delay effects; Dielectric films; Dielectric thin films; Kirchhoff´s Law; Silicon;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE
Conference_Location :
Santa Clara, CA
DOI :
10.1109/VMIC.1989.78029