Title :
A study of scaling effects on DRAM reliability
Author :
White, Mark ; Qin, Jin ; Bernstein, Joseph B.
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Abstract :
In this study, commercial 512 Mb Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) modules from three progressive technologies - 130 nm, 110 nm and 90 nm - were selected for experimentation to investigate degradation trends as a function of scaling. High temperature, high voltage accelerated stress testing was performed to characterize DRAM reliability and failure rates. Retention time degradation over time as a function of stress was also studied. For each technology generation, two distinct soft error populations were observed: Tail Distribution, characterized by randomly distributed weak bits with Weibull slope =1, and Main Distribution with Weibull slope greater than 1. Retention time was found to degrade exponentially with time. Analysis reveals multiple failure mechanisms are involved in retention tim e degradation. Activation energy was found to change with stress temperature for all three technologies. There are several observations with regard to scaling effects on DRAM reliability. First, the smaller the technology, the larger the operating current increases in percentage after high temperature, high voltage accelerated stress. Second, cell retention time variation decreases as technology scales down. Third, 90 nm DRAM has the largest soft-error failure rate among three technologies under equivalent stress, 110 nm DRAM has better reliability performance than 130nm at 55°C and 75°C, and 130nm DRAM is the best at 125°C. Studies con tinue into the scaling effects on reliability of progressive DRAM technologies.
Keywords :
DRAM chips; SRAM chips; Weibull distribution; failure analysis; integrated circuit reliability; integrated circuit testing; life testing; DDR SDRAM modules; DRAM reliability; Weibull slope distribution; activation energy; cell retention time variation; double data rate synchronous dynamic random access memory; high temperature high voltage accelerated stress testing; multiple failure mechanism analysis; retention time degradation; scaling effects; size 110 nm; size 130 nm; size 90 nm; soft-error failure rate; storage capacity 512 Mbit; tail distribution; temperature 125 degC; temperature 55 degC; temperature 75 degC; Acceleration; Degradation; Failure analysis; Random access memory; Reliability; Stress; Voltage control; DRAM; reliability; scaling; soft error; temperature; voltage;
Conference_Titel :
Reliability and Maintainability Symposium (RAMS), 2011 Proceedings - Annual
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-8857-5
DOI :
10.1109/RAMS.2011.5754522