Title :
Timing analysis with known false sub graphs
Author :
Belkhale, K.P. ; Suess, A.J.
Author_Institution :
AMBIT, Sunnyvale, CA, USA
Abstract :
In this paper we formulate the problem of timing analysis with known false sub graphs. This problem is important when we want the timing analysis system to take into account false path information that is supplied either by the user or by another program, and supply accurate timing information to optimization programs such as placement and wiring. We present an efficient algorithm for the problem.
Keywords :
circuit analysis computing; graph theory; logic CAD; logic circuits; logic design; timing; false path information; false sub graphs; placement; timing analysis; timing analysis algorithm; timing behavior; wiring; Algorithm design and analysis; Circuits; Delay; Information analysis; Latches; Logic; Timing; Wiring;
Conference_Titel :
Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-8200-0
DOI :
10.1109/ICCAD.1995.480255
