SCARM : A memory simulator with a compiler-assembler for the 32 bit ARM7 microprocessor

Author

Barahan, Nicole John A ; Custodio, John Jerico M ; Madamba, Joy Alinda R ; Roque, Christian Raymund K

Author_Institution

Intel Microprocessors Lab., Univ. of the Philippines Diliman, Quezon City, Philippines

fYear

2011

fDate

21-24 Nov. 2011

Firstpage

1409

Lastpage

1413

Abstract

This project is an implementation of a runtime memory simulator with a compiler-assembler for the ARM7 microprocessor with multi-core and floating point operation capability. Compiler support is extended to floating point computations. Also, the integrated development environment (IDE) features selective optimization for compilation. The target outputs are the assembly codes following the instruction set architecture (ISA) of the ARM7 and the equivalent binary instructions to generate the testbench for Synopsys VCS verification. The machine dependent optimizations of the compiler concentrate on register allocation and instruction scheduling techniques to further take advantage of the ARM7 architecture.

Keywords

instruction sets; microprocessor chips; multiprocessing systems; optimising compilers; program assemblers; scheduling; 32 bit ARM7 microprocessor; ARM7 architecture; SCARM; Synopsys VCS verification; compiler-assembler; floating point operation capability; instruction scheduling techniques; instruction set architecture; integrated development environment features selective optimization; multicore point operation capability; register allocation; runtime memory simulator; Assembly; Microprocessors; Optimization; Processor scheduling; Program processors; Registers; Resource management; ARM7; assembler; compiler; memory simulator;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2011 - 2011 IEEE Region 10 Conference

Conference_Location

Bali

ISSN

2159-3442

Print_ISBN

978-1-4577-0256-3

Type

conf

DOI

10.1109/TENCON.2011.6129041

Filename

6129041