Author :
Duriez, B. ; Tavel, B. ; Boeuf, F. ; Basso, M.T. ; Laplanche, Y. ; Ortolland, C. ; Reber, D. ; Wacquant, F. ; Morin, P. ; Lenoble, D. ; Palla, R. ; Bidaud, M. ; Barge, D. ; Dachs, C. ; Brut, H. ; Roy, D. ; Marin, M. ; Payet, F. ; Cagnat, N. ; Difrenza, R.
Abstract :
This paper demonstrates a full gate stack optimization by using post gate anneal (PGA) solution coupled with both germanium and fluorine gate predoping. We obtained a large carrier mobility enhancement for both NMOS (+50%) and PMOS (+20%) thanks to an important biaxial tensile stress generated by Ge predoping. Very simple and epitaxy-free, this architecture is directly compatible with both low power and high performance transistors. Competitive IonN = 1000μA/μm and IonP = 400μA/μm were found for Ioff = 100nA/μm at IV Vdd operation. Attractive matching factor AVT lower than 2.5 mV·μm has been obtained with poly grain size optimization. NBTI criteria have been successfully achieved thanks to a complementary Fluorine implant inside the P+ gate.
Keywords :
CMOS integrated circuits; annealing; carrier mobility; low-power electronics; 65 nm; CMOS high performance platform; CMOS low power platform; Ge predoping; IV Vdd operation; NBTI criteria; NMOS; P+ gate; PGA solution; PMOS; biaxial tensile stress; carrier mobility enhancement; fluorine gate predoping; fluorine implant; gate stack optimization; germanium gate predoping; low power transistors; matching factor; poly grain size optimization; post gate anneal; Capacitance-voltage characteristics; Degradation; Dielectrics; Electronics packaging; Germanium; Grain size; MOS devices; Rapid thermal annealing; Tensile stress; Transistors;
