• DocumentCode
    3004329
  • Title

    Shadow step structures for the analysis of thin film conductors

  • Author

    Rosvold, Warren C.

  • Author_Institution
    Signetics Corp., Sunnyvale, CA, USA
  • fYear
    1989
  • fDate
    12-13 Jun 1989
  • Firstpage
    274
  • Lastpage
    281
  • Abstract
    A description is given of research on shadow step structures (3S), which are prepatterned, mesa-type geometries that are electrically self-isolating and self-aligning when overlaid with a conducting film. This basic mesa topography has been historically used as a disposable medium for lift-off metallization and other generic patterning forms. A modification of this technique has recently been useful in providing an analytic tool for the maskless evaluation of as-deposited thin-film conductors. On an experimental basis, 3S is being used as an intermediate means to verify the sheet resistivity and tempco of sichrome resistor films. Also, the formation of electromigration patterns is used as a simplified, nonintrusive alternative to the current fabrication method. The 3S technique is being evaluated for other QTAT analyses including the quantifying of physical film stress and Schottky diodes, together with other bulk silicon devices which evaluate metal-silicon interfaces
  • Keywords
    VLSI; metallisation; semiconductor-metal boundaries; thin film resistors; QTAT analyses; Schottky diodes; Si-Co films; TCR; VLSI; analysis of thin film conductors; analytic tool; as-deposited thin-film conductors; electrically self-isolating; electromigration patterns; fabrication method; maskless evaluation; mesa topography; mesa-type geometries; metallization; multilevel interconnection; physical film stress; self-aligning; shadow step structures; sheet resistivity; sichrome resistor films; tempco; temperature coefficient; Conductive films; Conductivity; Electromigration; Fabrication; Geometry; Metallization; Resistors; Semiconductor films; Surfaces; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE
  • Conference_Location
    Santa Clara, CA
  • Type

    conf

  • DOI
    10.1109/VMIC.1989.78031
  • Filename
    78031